1. Field of the Invention
The present invention relates to semiconductor combinational logic circuits such as are employed in programmable logic devices (PLDs), and particularly to such a logic circuit which is programmable to provide any selected combinational logic function of a plurality of logic signals.
2. Description of the Related Art
A programmable logic device (PLD) is an integrated circuit having a large number of gates which can be programmably interconnected so as to provide a selected logic function. Such devices are available in bipolar, MOS and CMOS technologies, bipolar providing higher speed and MOS (particularly CMOS) having the advantage of lower power consumption. User programmability to establish the appropriate interconnections for a selected logic function may be achieved, for example, by supplying address signals to such interconnections which serves to open fusible links or establish charges on the gates of MOS or CMOS devices. Further description of PLDs can be found, for example, in U.S. Pat. No. 4,442,072, issued Dec. 20, 1983, U.S. Pat. No. 4,257,745, issued Feb. 16, 1988, and in the text "The Art of Electronics" by Horowitz et al, Cambridge Univ. Press, 2nd Edition, 1989, pp. 501-505. A problem encountered with PLDs is that in order to be capable of providing a large variety of selectable logic functions a large number of fixed logic gates are necessary. Consequently, when programmed for a particular logic function, many of such gates are not used and so the circuit utilization efficiency is very low. The present invention reduces the requisite number of logic gates in order to obtain all possible logic function of a plurality of logic signals.